`include "inc.vh"

// module counter(
// 	input 		   logic rst, clk,
// 	output 		   logic [7:0] count);

//    always_ff@(posedge rst, posedge clk)
//      begin
// 		if(rst) 
// 		  count <= 8'h00;
// 		else
// 		  count <= count + 8'h01;
//      end
// endmodule // counter

module counter(
			   input 			rst, clk,
			   output reg [7:0] count);

   always@(posedge rst, posedge clk)
     begin
		if(rst) 
		  count <= 8'h00;
		else
		  count <= count + 8'h01;
     end
endmodule // counter